mirror of
https://github.com/HarbourMasters/Starship.git
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121 lines
4.8 KiB
Plaintext
121 lines
4.8 KiB
Plaintext
// Signal Processor Registers
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SP_MEM_ADDR_REG = 0xA4040000; // defined:True
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SP_DRAM_ADDR_REG = 0xA4040004; // defined:True
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SP_RD_LEN_REG = 0xA4040008; // defined:True
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SP_WR_LEN_REG = 0xA404000C; // defined:True
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SP_STATUS_REG = 0xA4040010; // defined:True
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SP_DMA_FULL_REG = 0xA4040014; // defined:True
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SP_DMA_BUSY_REG = 0xA4040018; // defined:True
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SP_SEMAPHORE_REG = 0xA404001C; // defined:True
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SP_PC = 0xA4080000; // defined:True
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// Display Processor Command Registers / Rasterizer Interface
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DPC_START_REG = 0xA4100000; // defined:True
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DPC_END_REG = 0xA4100004; // defined:True
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DPC_CURRENT_REG = 0xA4100008; // defined:True
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DPC_STATUS_REG = 0xA410000C; // defined:True
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DPC_CLOCK_REG = 0xA4100010; // defined:True
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DPC_BUFBUSY_REG = 0xA4100014; // defined:True
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DPC_PIPEBUSY_REG = 0xA4100018; // defined:True
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DPC_TMEM_REG = 0xA410001C; // defined:True
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// Display Processor Span Registers
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DPS_TBIST_REG = 0xA4200000; // defined:True // DPS_TBIST_REG / DP_TMEM_BIST
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DPS_TEST_MODE_REG = 0xA4200004; // defined:True
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DPS_BUFTEST_ADDR_REG = 0xA4200008; // defined:True
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DPS_BUFTEST_DATA_REG = 0xA420000C; // defined:True
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// MIPS Interface Registers
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MI_MODE_REG = 0xA4300000; // defined:True // MI_MODE_REG / MI_INIT_MODE_REG
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MI_VERSION_REG = 0xA4300004; // defined:True
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MI_INTR_REG = 0xA4300008; // defined:True
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MI_INTR_MASK_REG = 0xA430000C; // defined:True
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// Video Interface Registers
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VI_STATUS_REG = 0xA4400000; // defined:True // VI_STATUS_REG / VI_CONTROL_REG
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VI_DRAM_ADDR_REG = 0xA4400004; // defined:True // VI_DRAM_ADDR_REG / VI_ORIGIN_REG
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VI_WIDTH_REG = 0xA4400008; // defined:True
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VI_INTR_REG = 0xA440000C; // defined:True
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VI_CURRENT_REG = 0xA4400010; // defined:True
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VI_BURST_REG = 0xA4400014; // defined:True // VI_BURST_REG / VI_TIMING_REG
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VI_V_SYNC_REG = 0xA4400018; // defined:True
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VI_H_SYNC_REG = 0xA440001C; // defined:True
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VI_LEAP_REG = 0xA4400020; // defined:True
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VI_H_START_REG = 0xA4400024; // defined:True
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VI_V_START_REG = 0xA4400028; // defined:True
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VI_V_BURST_REG = 0xA440002C; // defined:True
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VI_X_SCALE_REG = 0xA4400030; // defined:True
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VI_Y_SCALE_REG = 0xA4400034; // defined:True
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// Audio Interface Registers
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AI_DRAM_ADDR_REG = 0xA4500000; // defined:True
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AI_LEN_REG = 0xA4500004; // defined:True
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AI_CONTROL_REG = 0xA4500008; // defined:True
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AI_STATUS_REG = 0xA450000C; // defined:True
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AI_DACRATE_REG = 0xA4500010; // defined:True
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AI_BITRATE_REG = 0xA4500014; // defined:True
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// Peripheral/Parallel Interface Registers
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PI_DRAM_ADDR_REG = 0xA4600000; // defined:True
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PI_CART_ADDR_REG = 0xA4600004; // defined:True
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D_A4600005 = 0xA4600005; // defined:True // TODO figure out its name
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D_A4600006 = 0xA4600006; // defined:True // TODO figure out its name
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D_A4600007 = 0xA4600007; // defined:True // TODO figure out its name
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PI_RD_LEN_REG = 0xA4600008; // defined:True
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PI_WR_LEN_REG = 0xA460000C; // defined:True
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PI_STATUS_REG = 0xA4600010; // defined:True
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PI_BSD_DOM1_LAT_REG = 0xA4600014; // defined:True // PI dom1 latency
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PI_BSD_DOM1_PWD_REG = 0xA4600018; // defined:True // PI dom1 pulse width
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PI_BSD_DOM1_PGS_REG = 0xA460001C; // defined:True // PI dom1 page size
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PI_BSD_DOM1_RLS_REG = 0xA4600020; // defined:True // PI dom1 release
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PI_BSD_DOM2_LAT_REG = 0xA4600024; // defined:True // PI dom2 latency
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PI_BSD_DOM2_LWD_REG = 0xA4600028; // defined:True // PI dom2 pulse width
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PI_BSD_DOM2_PGS_REG = 0xA460002C; // defined:True // PI dom2 page size
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PI_BSD_DOM2_RLS_REG = 0xA4600030; // defined:True // PI dom2 release
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// RDRAM Interface Registers
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RI_MODE_REG = 0xA4700000; // defined:True
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RI_CONFIG_REG = 0xA4700004; // defined:True
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RI_CURRENT_LOAD_REG = 0xA4700008; // defined:True
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RI_SELECT_REG = 0xA470000C; // defined:True
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RI_REFRESH_REG = 0xA4700010; // defined:True
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RI_LATENCY_REG = 0xA4700014; // defined:True
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RI_RERROR_REG = 0xA4700018; // defined:True
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RI_WERROR_REG = 0xA470001C; // defined:True
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// Serial Interface Registers
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SI_DRAM_ADDR_REG = 0xA4800000; // defined:True
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SI_PIF_ADDR_RD64B_REG = 0xA4800004; // defined:True
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D_A4800008 = 0xA4800008; // defined:True // reserved
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D_A480000C = 0xA480000C; // defined:True // reserved
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SI_PIF_ADDR_WR64B_REG = 0xA4800010; // defined:True
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D_A4800014 = 0xA4800014; // defined:True // reserved
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SI_STATUS_REG = 0xA4800018; // defined:True
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LEO_CMD = 0xA5000508;
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LEO_STATUS = 0xA5000508;
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LEO_BM_CTL = 0xA5000510;
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LEO_BM_STATUS = 0xA5000510;
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LEO_SEQ_CTL = 0xA5000518;
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LEO_SEQ_STATUS = 0xA5000518;
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LEO_C2_BUFF = 0xA5000000;
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LEO_SECTOR_BUFF = 0xA5000400;
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LEO_DATA = 0xA5000500;
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LEO_MISC_REG = 0xA5000504;
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LEO_CUR_TK = 0xA500050C;
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LEO_ERR_SECTOR = 0xA5000514;
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LEO_CUR_SECTOR = 0xA500051C;
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LEO_HARD_RESET = 0xA5000520;
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LEO_C1_S0 = 0xA5000524;
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LEO_HOST_SECBYTE = 0xA5000528;
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LEO_C1_S2 = 0xA500052C;
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LEO_SEC_BYTE = 0xA5000530;
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LEO_C1_S4 = 0xA5000534;
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LEO_C1_S6 = 0xA5000538;
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LEO_CUR_ADDR = 0xA500053C;
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LEO_ID_REG = 0xA5000540;
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LEO_TEST_REG = 0xA5000544;
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LEO_TEST_PIN_SEL = 0xA5000548;
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LEO_RAM_ADDR = 0xA5000580;
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